Crosstalk can cause differences in signal arrival times, i.e., can cause the signal to arrive too early or too late. Static timing analysis involves analyzing whether or not a signal arrives too late or too early so that the signal is sampled at the right time. In order for a design to work effectively, a signal should arrive within a certain window.
Some degree of crosstalk typically exists in every net of a design. Thus, a signal is delayed in every net, and if there are multiple nets, the signal delay can be increased significantly. A conventional way to determine a worst case probability for the signals is, for example, to determine the probability on each net and summed together. However, the worst case scenario rarely occurs, and users have complained that such a model is not desirable because it is too aggressive for something that does not occur that often.
Conventional noise-on-delay analysis assumes that the worst-case scenario realizable under timing windows and other constraints happens necessarily. This causes cumulative crosstalk delay on critical timing path to be too pessimistic, thereby resulting in difficulties in timing closure. As an example, consider a design in which the most critical path contains 33 logic stages, with 151 total aggressors spread out over those logic stages. Existing timing analysis with crosstalk assumes all 151 aggressors will switch in the opposite direction as their corresponding victims, and also switch at the precise timing with respect to the victim so as to cause the worst case impact on path delay. All of this must happen simultaneously in the same clock cycle. This scenario is very unrealistic, and it is a major reason for difficulties in achieving timing and signal integrity (SI) closure. This is illustrated in FIG. 1, in which the noise contribution of each of the 151 aggressors on the critical path is expressed in glitch noise as percentage of Vdd. The cumulative glitch noise of all aggressors is 76.4% of Vdd, whereas the statistical distribution gives a maximum of only 36% of Vdd with 99% certainty. In real-world designs, this percentage could be much higher due to switching probabilities being much less than 1.0, and the worst case switching alignment probabilities also much less than 1.0. In other words, only 47% of the total crosstalk impact on path delay may be statistically achievable.
Therefore, there is a need for an improved approach for implementing crosstalk analysis, which addresses and improves upon the above-described problems with conventional approaches.